LCLS-II Timing System and Synchronous Bunch Data Acquisition
453
C. Bianchini Mattison, K.H. Kim, P. Krejcik, M. Weaver, S. Zelazny
SLAC, Menlo Park, California, USA
The new timing system for the LCLS-II SC linac and FEL meets the challenging requirements for delivering multiple interleaved timing patterns to a number of different destinations at rates up to 1 MHz. The timing patterns also carry information on bunch charge and beam energy to prevent inadvertent selection of beam dumps beyond their rated beam power. Beamline instruments are equipped with a timing receiver that performs bunch-by-bunch synchronous data acquisition based on the timing pattern for that location. Data is buffered in on-board memory for up to 106 machine pulses (1 second at 1 MHz). The large data volume can be locally processed and and analysed before transmission to clients on the network. Commissioning and experience with the new system will be presented.
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A Novel Cavity BPM Electronics for SHINE Based on RF Direct Sampling and Processing
458
L.W. Lai, S.S. Cao, X.Q. Liu, Y.M. Zhou
SARI-CAS, Pudong, Shanghai, People’s Republic of China
J. Chen
SSRF, Shanghai, People’s Republic of China
R. Meng
SINAP, Shanghai, People’s Republic of China
Funding:Work supported by The National Science Foundation of China (Grant No.12175293). Youth Innovation Promotion Association, CAS (Grant No. 2019290) A RF direct sampling beam signal processor has been developed in SSRF. It mainly consists of four channels RF direct sampling ADCs and a SoC FPGA. The ADC is 9 GHz bandwidth and 2.6 GHz sampling rate. A prototype of RF module contains band pass filter, low noise amplifier and step attenuator has been designed for SHINE cavity BPM system. Then a novel cavity BPM electronic including the processor and the RF module has been built for SHINE. The performance of the electronic has been analyzed and evaluated in lab. The amplitude relative error is 2.0×10-4,which is better than the required 1×10-3 on cavity BPM system. The phase error is 14 fs, also bet-ter than the requirement of RF BAM system. The algorithm and the implementation in FPGA have been introduced. Corresponding author: lailw@sari.ac.cn
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The Development of a 128-Channel Ultra-Low Noise Trans-Impedance Amplifier System
W. Tian
IMP/CAS, Lanzhou, People’s Republic of China
A new 128-channel readout electronics system is designed for the bunch-by-bunch profile measurement of High-Intensity Heavy-ion Accelerator Facility (HIAF), and Booster Ring (BRing). This system consists of 128 ultra-low noise analog front-ends (AFE), 16 8-channel 60 Msps simultaneous sampling analog-digital conversions (ADC), 8 Kintex-7 field-programmable gate arrays (FPGA), and a Zynq FPGA. It is capable of monitoring weak current signals of 25 pA÷1.8 μA. The Kintex-7 FPGA is an intermediate buffer stage, designed to decode the ADC’s serial output data, and to perform digital signal processing algorithms. Finally, the Zynq FPGA performs data aggregation, beam profile fitting, and data interaction with the host computer. During offline tests, the effective number of bits (ENOB) is better than 12 bits, and the nonlinearity is less than 0.2% on a full scale. Finally, the system is deployed for the beam profile measurement. The obtained peak value shows a good proportionality with the beam intensity increment, and all the electronics’ properties achieve reasonable and excellent performance.
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